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november 2013 ? 20 13 fairchild semiconductor corporation www.fairchildsemi.com FAN8060 ? rev. 1.0. 1 f an 8060 ? 1.2 mhz, 1 a sy nchronous step - down dc/dc regulator f an 8060 1.2 mhz, 1 a synchronous step -d own dc/dc regulator features ? current mode control ? over 9 6 % efficient ? selectable continuous output current: 500 m a/ 1 a ? 2.5 v to 5.5 v input voltage range ? output voltage as low as 1.2 v ? 1.2 mhz operating frequenc y ? less than 1 a shutdown current ? external synchronization from 500 khz to 2 mhz ? 100 % duty cycle ? synchronous switching fet; no schottky diode required ? stable with ceramic c apacitors ? light l oad m ode with pulse skipping ? external compensation ? external so ft- start ? overload / short - circuit protection ? under - voltage lockout ? thermal shutdown ? 10- lead 3x3 mm green mlp package applications ? pdas ? gps devices ? mp3 players ? mini pci ? digital cameras ? peripheral ports ? dsp core ? usb devices ? pcmcia ? cable modem ? data cards description the FAN8060 is a highly efficient , monolithic , current - mode , step - down synchronous regulator . it can provide 1 a continuous current from 2.5 v to 5.5 v i nput voltage . the output voltage can be adjusted from 1.2 v up to the i nput vo ltage with an external voltage divider. external compensation and soft - start allow for design optimization and flexibility. high - frequency operation allows for all - ceramic solutions and small footprints . in addition, a user - selectable current limit provid es protection against output overload and short circuit. FAN8060 features pulse skipping to achieve higher efficiency during light load operation. 100% duty cycle capability enables power solutions to extend the drop out voltage. provision for external syn chronization allows users to minimize input capacitors and manage emi in solutions . FAN8060 is available in a green, low profile , 10-lead 3x3 mm mlp package . en FAN8060 ss comp pvin avin fb pgnd sw agnd sync c out l out c ss input 2.5 to 5.5v hi lo c c r c c a r2 r3 output 1.2v to 5.5v c in figure 1. typical application circuit ordering i nformation part number operating temperature range package packing method FAN8060empx - 40 to +85c 10- pin, 3x3 mm molded leadless package (mlp) tape & reel for fairchild?s definition of ?green? eco status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html .
? 20 13 fairchild semiconductor corporation www.fairchildsemi.com FAN8060 ? rev. 1.0. 1 2 f an 8060 ? 1.2 mhz, 1 a synchronous step - down dc/dc regulator pin configuration en 1 2 3 4 5 6 7 8 9 10 avin sw pvin pgnd sync ss comp fb agnd figure 2. pin configuration (t op view) note: 1. c onnect e xposed pad to a gnd pin definitions pin name function 1 en e nable . enables op erat ion when pulled to logic high . 2 avin analog i nput v oltage . all internal control circuits are connected to this supply. 3 pvin power input voltage . power stage s upply voltage . 4 sw switching node . the drains of both pmos and n mos. 5 pgnd power gro und . power return and source of the power nmos 6 sync synchronization . use this pin to synchronize the part to an external clock. this pin also controls current limit threshold. t ie to ground for 1. 0 a or tie to v in for 0. 5 a continuous load current . wh en an external clock is applied, the default current setting is 1 a. this pin has a pull - down resistor of 450 k? . 7 ss soft -s tart . a capacitor connected between this pin and a gnd can set soft - start time. 8 comp compensation . error a mp lifier output. connect the external compensation network between this pin and agnd . 9 fb output voltage feedback . connect through a resistor divider to set the output voltage. 10 agnd analog g round . ground return for all internal control circuits.
? 20 13 fairchild semiconductor corporation www.fairchildsemi.com FAN8060 ? rev. 1.0. 1 3 f an 8060 ? 1.2 mhz, 1 a synchronous step - down dc/dc regulator absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be oper able above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings ar e stress ratings only. all voltage values, except differential voltages, are given with respect to the network ground terminal. stress beyond those listed under absolute maximum ratings may cause permanent damage to the device. symbols parameter min. max . unit v pvin pvin (agnd = pgnd) - 0.3 6 .0 v v avin avin (agnd = pgnd) - 0.3 6 .0 v v sw s witch voltage, sw to gnd - 0.3 v in + 0.3 or 6 .0 v all other pins except comp - 0.3 6 .0 v t stg storage temperature -65 +150 c t j junction temperature -40 + 125 c esd electrostatic discharge protection human body model , jesd22 - a114 2.0 kv charged device model , jesd22 - c101 2.5 note: 2. comp pin has an internal clamp to 1.5 v. recommended operating conditions the recommended operating conditions table defines the c onditions for actual device operation. recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter min . max. unit v in supply voltage 2.5 5.5 v t a ambient operating temperature -40 +85 c thermal information symbol parameter min. typ. max. units t stg storage temperature -65 +150 c t l lead soldering temperature, 30 sec onds +300 c ja thermal res istance: junction -to - ambient 49 c/w jc thermal resistance: junction -to - case ( 3 ) 8 c/w p d total power dissipation in the package, t a =25c ( 3 ) 1.3 w note: 3. typical thermal resistance when mo unted on a four - layer pcb. actual results are dependent upon mounting method and surface related to the design.
? 20 13 fairchild semiconductor corporation www.fairchildsemi.com FAN8060 ? rev. 1.0. 1 4 f an 8060 ? 1.2 mhz, 1 a synchronous step - down dc/dc regulator electrical characteristics v in = 5.0 v, v out = 2.5 v, c out = 10 f, c in = 10 f , over operating range , unless otherwise noted . symbol parameter c onditions min. typ. max. units basic operation v in v in operating voltage avin = pvin 2.5 5.5 v i q quiescent current v e n =5 v, v ss = 0 v 250 371 500 a i sd shutdown current v e n =0 v 0.3 4 0. 6 0 a v uvlo v in under - voltage lockout rising v in 2.1 0 2. 19 2. 2 5 v v uvlohys v in under - voltage lockout hysteresis 70 mv v enh enable high input voltage 1. 70 2 .00 v v enl enable low input voltage 0.8 0 1.22 v r onpmos pmos on resistance ( 4 ) v in = 5 v 200 m ? v in = 3.3 v 300 r onnmos nmos on resistance ( 4 ) v in = 5 v 200 m ? v in = 3.3 v 3 0 0 i lim p- channel current limit v fb = 0.7 v, v in =5 v, 100% d uty c ycle v sync = 0 v 1.2 a v sync = v in 0.6 f osc oscillator frequency t a = 25c 1. 1 05 1.2 1 0 1. 350 m h z v sync sync threshold rising edge v in /2 v f sync synchronization frequency v sync = square wave 500 2000 khz t sync min imum s ync p ulse w idth v sync on time 100 ns i amp error amplifier sink/source current 3 0 45 60 a g ea ( 4 ) 7 00 1000 1 400 a/v a vea ( 4 ) 550 v/v g cs current sense gain ( 4 ) 3 a/v v ref reference voltage f or t emperature c o - efficient , s ee figur e 12 measured at f b pin t a = 25c 1. 181 1. 205 1.2 2 9 v i fb fb bias current t a =25 c -0. 10 - 0.0 6 0 a i ss soft - start current - 5.5 -4 . 5 - 3.5 a protections t otp over - temperature threshold ( 4 ) + 165 c t hys over - temper ature hysteresis + 20 c note: 4. guaranteed by d esign and characterization ; n ot production tested.
? 20 13 fairchild semiconductor corporation www.fairchildsemi.com FAN8060 ? rev. 1.0. 1 5 f an 8060 ? 1.2 mhz, 1 a synchronous step - down dc/dc regulator functional block diagram o sc ill a t o r log i c & d r i ve r c u rre n t s e n s e s l ope c o m p e n sat i o n e n a b l e & r e f e r e n c e p w m lo w c u rr e n t d e t ec t v r e f 4 u a + + + + - - - s ho r t c i r c u i t p r o t ec t i o n e n sy n c s s f b c o m p a g n d p g n d s w pv i n g m a v i n 45 0 k p u l s e s k i p + + + + - - + o t p to i n t e r n a l s uppl y 1 . 4 v figure 3. functional block diagram
? 20 13 fairchild semiconductor corporation www.fairchildsemi.com FAN8060 ? rev. 1.0. 1 6 f an 8060 ? 1.2 mhz, 1 a synchronous step - down dc/dc regulator operation description the FAN8060 is a step - down converter operating in current - mode pwm archite cture with a typical switching frequency of 1.2 mhz. at the beginning of each clock cycle, the p - channel transistor is turned on. the current in the inductor ramps up and is sensed via an internal circuit. the p - channel switch is turned off when the sensed current causes the pwm comparator to trip, which is when the output voltage is in regulation or when the inductor current reaches the current limi t (set internally to 1.2 a, typical ly ). after a minimum dead time to prevent shoot - through current, the n - cha nnel transistor is turned on and the current ramps down. as the clock cycle is completed, the n - channel switch is turned off and the next clock cycle starts. light load operation as the output load reduces , the cu rrent in the inductor during off time is s ensed across the low side mosfet . when the current reverses direction, the low - side mosfet is turned off and the high - side mosfet is not turned on un til the output is out of regulation. 100% duty cycle operation as the input voltage approaches the output voltage, the controller start s to increase the duty cycle to maintain output regulation until duty cycle reaches 85%. the controller then transition s to a 100% duty cycle mode over several cycles to support the load . when the dropout condition is met , the converter turn s the p - channel high side continuously on. in this mode, the output voltage is equal to the input voltage , minus the voltage drop across the p - channel mosfet. soft start when the input voltage on avin exceeds the uvlo threshold and en is h igh, the circuit releases ss and enables the pwm regulator. a capacitor connected to the ss pin and agnd is charged by a 4 a internal current source, causing the voltage on the capacitor to rise. when this voltage reaches 1.2 v, the output is in regulatio n. the ss voltage continue s to rise to avin . the time for the output to reach regulation is given by the following equation: v a nf c ms t ss 2 . 1 / 4 ) ( ) ( p ( 1 ) output overload and short - circuit protection is active during so ft- start. when the part is disabled, ss pin is pulled low internally. over l oad & short - circuit protection f an 8060 employs cycle -by - cycle current limiting, which limit s current by reducing duty cycle during overload. as the load increase s beyond the limit, the output voltage starts to reduce , thereby reducing the fb voltage . when the fb node is half the refer e nce voltage and the comp node has reached maximum value, short - circuit protection is detected. at that time , both the ss pin and the comp pin are pulle d to ground until the inductor current crosses zero. at th at point, both ss and comp are released for the current to ramp up again. this continues until the short - circuit condition is released.
? 20 13 fairchild semiconductor corporation www.fairchildsemi.com FAN8060 ? rev. 1.0. 1 7 f an 8060 ? 1.2 mhz, 1 a synchronous step - down dc/dc regulator typical performance characteristics v in =5 v, v out = 2 .4 v, l=3 . 3 h , c in =10 f, c out = 10 f, f s =1.2 mh z , t a =25 c, unless otherwise noted. figure 4. en s tartup with 1 a load figure 5. en turn off with 1 a load figure 6. pwm operation with 1 a load figure 7. 2 mhz sync operation with 1 a load figure 8. load t ransient r es ponse(step - up/down) figure 9. output vo ltage r ipple with 1 a load i l ( (1 a/div.) v out (2v/div.) v sw (2v/div.) en(2v/div.) [ 1ms/div. ] v sw (2v/div.) v sw (2v/div.) v sw (2v/div.) v out (10mv/div. ac coupled) v out (2v/div.) v out ( 5 0mv/div . ac coupled ) i l ( (1 a/div.) i l ( (1 a/div.) v out (2v/div.) i l ( (1 a/div.) i out (500m a/div.) slew rate : 2.5a/us [ 1ms/div. ] i l ( (1a/div.) v out (2v/div.) v sw (2v/div.) en(2v/div.) [500n s/div. ] [2 0 0 ns/div. ] [2 00 s/div. ] [500n s/div. ]
? 20 13 fairchild semiconductor corporation www.fairchildsemi.com FAN8060 ? rev. 1.0. 1 8 f an 8060 ? 1.2 mhz, 1 a synchronous step - down dc/dc regulator typical performance characteristics (continued) v in =5 v, v out = 2.4 v, l=3.3 h, c in =10 f, c out = 10 f, f s =1.2 m h z , t a =25 c , unless otherwise noted. -0.30 -0.25 -0.20 -0.15 -0.10 -0.05 0.00 0.05 0.10 0 0.2 0.4 0.6 0.8 1 80 83 86 89 92 95 98 0 0.2 0.4 0.6 0.8 1 figure 10. normalized v out vs. load cur rent figure 11. efficiency vs. load current -4.00 -2.00 0.00 2.00 4.00 -50 -25 0 25 50 75 100 figure 12. normalized v ref vs. temperature figure 13. normalized oscillation frequency vs. t emperat ure load current [a] efficiency [%] load current [a] v out [%] 3.3v in /2.4v o 5 v in /2.4v o 3.3v in /2.4v o 5 v in /2.4v o temperature [ ] temperature [ ] v ref [ % ] frequency [ % ]
? 20 13 fairchild semiconductor corporation www.fairchildsemi.com FAN8060 ? rev. 1.0. 1 9 f an 8060 ? 1.2 mhz, 1 a synchronous step - down dc/dc regulator applications information r efer to figure 1 for reference designators . output voltage setting t he output voltage of the FAN8060 can be set from 1.2 v to v in by an external resistor divider, given by the following equation : ) 1 ( 2 . 1 3 2 r r v out + = ( 2 ) w here , v out equals the o utput voltage . inductor selection typically , the inductor value is chosen based on ripple current ( ? i l ), which is chosen between 10 % and 35% of the maximum dc load. regulator designs that require fast transient response use a higher ripple - current setting , while regulator designs that requ ire higher efficiency keep ripple current on the low side and operate at a lower switching frequency. for a given output voltage ripple requirement, l can be calculated by the following equation : s l out f i d v l ? ? ? ? ) 1 ( ( 3 ) w here ; d = duty ratio (v o /v in ); f s = switching frequency ; and i l = inductor ripple value, typically set to 1 0% - 3 5% of the maximum steady - state load current . the inductor should have a low dcr to minimize the conduction losses and maximize eff iciency. some recommended inductors are suggested in table 1 : table 1. recommended i nductor s (3.3 h) size[mm2] dcr part n umber vendor 7x7x3 23 m ? slf7032t - 3r3 tdk 5x5x2 60 m ? ltf5022t - 3r3 tdk 4x4x2 78 m ? vlcf4020t -3r 3 tdk 2.6x2.8x1.2 130 m ? vlf3012at - 3r3 tdk output capacitor selection the output capacitor is selected based on the needs of the final application and its output ripple requirements. a larger output capacitor value reduces the output ripple voltage. the formula of output ripple v out is : ? ? ? ? ? ? ? ? ? ? + ? ? ? s out l out f c esr i v 8 1 ( 4 ) w here c out is the output capacitor. esr is the equivalent series resistance of the output capacitor. input capacitor selection the input capacitor redu ces the rms current drawn from the input and switching noise from the device. the combined rms current rating for the input capacitor should be greater than the value calculated by the following equation : ) ( 2 d d i i outmax rms ? ? = ( 5 ) where: i rms = rms current of the input capacitor ; and i outmax = maximum output current . s mall , h igh value , inexpensive, lower - esr ceramic capacitors are recommended ; 10 f ceramic capacitors with x7r or x5r should be adequate for 1 a app lication s . loop compensation the loop is compensated using a feedback network connected between comp and agnd. figure 14 shows a type - 2 compensation network used to stabilize the FAN8060. c a v out v ref c c r c r2 r3 - + v fb g m v e figure 14. compensation n etwork the goal of th e compensation design is to shape the frequency response of the converter to achieve high dc gain and fast transient , while maintaining loop stability. fan8 060 employs peak - current - mode control for easy use and fast transient response. current mode control helps s implif y the loop to a one - pole and one zero system. the dc gain of the voltage feedback loop is given by: out fb vea cs l vdc v v a g r a ? ? ? = ( 6 ) w here : a vdc = dc gain of the feedback loop ; r l = l oad resistor value (v o ut /i out ); g cs = c urrent sense gain (3 a/v) ; a vea = e rror amplifier voltage gain (550 v/v) ; and v fb = feedback threshold voltage (1.2 v).
? 20 13 fairchild semiconductor corporation www.fairchildsemi.co m f an 8060 ? rev. 1.0. 1 10 f an 8060 ? 1.2 mhz, 1 a synchronous step - down dc/dc regulator the system pole is calculated by the equation: l out p r c f ? ? = 2 1 1 ( 7 ) the system zero is due to the output capacitor and its esr . system zero is calculated by the equation: esr c f out z ? ? = 2 1 1 ( 8 ) the output characteristics of the error (gm) amplifier are controlled by a series capacitor and resistor network connected at the comp pin to gnd. the p ole is calculated by the following equation: vea c ea p a c g f ? ? = 2 2 ( 9 ) w here : g ea = error amplifier transconductance (1000 a/v ); and c c = compensation capacitor. zero is due to the compensation capacitor (c c ) and resistor (r c ) calculated by the following equation: c c z r c f ? ? = 2 1 2 ( 10) w here r c is compensation resistor. the system crossover frequency (f c ), where the control loop has unity gain , is recommended to be set at 1/10 th of switching frequency. generally , higher f c means faster response to load transient s , but can result in instability if not properly compensated. the f i r st step in co mpensation design is choosing the compensation resistor (r c ) to s et the crossover frequency by the following equation: fb ea cs out c out c v g g v f c r ? ? ? ? ? = 2 ( 11) w here v fb is reference voltage. the n ext step is choosing the co mpensation capacitor (c c ) to achieve the desired phase margin. for a pplications with typical inductor values, setting the compensation zero, f z 2 , to below one fourth of the crossover frequency provides sufficient phase margin. determine the (c c ) value by t he following equation : c c c f r c ? ? = 2 ( 12) then d etermine if the second compensation capacitor (c a ) is required. it is required if the e sr zero of the output capacitor is located at less than half of the switching frequency . 2 2 1 s out f esr c < ? ? ( 13) if required , add the second compensation capacitor (c a ) to set the pole f p 3 at the location of the esr zero. determine (c a ) value by the equation : c out a r esr c c ? = ( 14) design e xample table 2 provides component values for delivering various output voltages with loads up to 1 a with v in at 5 v ( 10% toleran ce) . table 2. recommended feedback a nd compensation values (v in = 5 v) v o c 4 l 1 r 2 r 3 r 1 c 5 c 2 1.2 v 10 f 3. 3 h short open 4.7 k ? 1.5 nf 150 pf 1.5 v 2.55 k ? 10.2 k ? 1.8 v 5.9 k ? 11.8 k ? 2.5 v 16.2 k ? 15 k ? 3.3 v 18.7 k ? 10.7 k ? en FAN8060 ss comp pvin avin fb pgnd sw agnd sync c4 10f l1 3.3h c1 10nf input 2.5 to 5. 5v hi lo c5 1.5nf r1 4.7k c2 150pf r2 16.2k r3 15k output 2.5v/1a c3 10f figure 15. recommended schematic (5 v in to 2.5 v o )
? 20 13 fairchild semiconductor corporation www.fairchildsemi.co m f an 8060 ? rev. 1.0. 1 11 f an 8060 ? 1.2 mhz, 1 a synchronous step - down dc/dc regulator pcb layout recommendations the switching power supply pc b layout needs careful attention and is critical to achieving low losses and clean and stable operation. although each design is different, below are some general recommendations for a good pcb layout . ? keep the high - current traces and load connectors as sh ort and wide as possible. these traces consist of vin, gnd, vout , and sw . ? place the input capacitor, the inductor , and the output capacitor as close as possible to the ic terminals. ? keep the loop area between sw node, i nductor , and output capacitors as sm all as possible ; minimizing ground loops to reduce emi issues. ? route high - dv/dt signals, such as sw node, away from the error amplifier input/output pins. ? keep components connected to the fb and comp pins close to the pin s . figure 16. recommended pcb layout
1.55 3.10 0.23 0.02 2.20 0.55 0.78 2.33 2.00 0.25 2.25 2.00 0.50 0.20 0.05 0.00 0.80 max side view seating plane c 3.0 3.0 2x top view 2x 0.10 c a b 3.10 2.90 1.60 1.50 2.30 2.20 0.38 0.30 0.20 0.45 0.35 0.5 3.10 2.90 2.0 pin #1 ident bottom view land pattern recommendation notes: a. conforms to jedec registration mo-229, variation weed-5 b. dimensions are in millimeters c. dimensions and tolerances per asme y14.5m, 2009 d. land pattern dimensions are nominal reference values only e. drawing filename: mkt-mlp10brev2 d 10 6 1 5 6 10 1 5 0.10 c 0.08 c 0.10 c 0.10 m c a b 0.05 m c
www. onsemi.com 1 on semiconductor and are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries i n the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . a listing of on semiconductor?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent ? marking.pdf . on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does o n semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including ?typic als? must be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the right s of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semicondu ctor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distrib utors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 www.onsemi.com literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative ? semiconductor components industries, llc

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